Type:

Other

Description:

This lab activity from the Digital Logic Project is designed to familiarize students with using many of the common aspects of the Quartus II software for digital logic design. Students will create a new project, create a new vhdl file, use the MegaWizard Plug-In Manager, compile the design, plan and manage I/O assignments, apply timing analysis using the TimeQuest Timing Analyzer, write Synopsys Design Contraint (SDC) files, and program a design onto the Altera DE2 Development Board.

Subjects:

  • Science > Engineering
  • Science > Technology
  • Education > General

Education Levels:

  • Grade 1
  • Grade 2
  • Grade 3
  • Grade 4
  • Grade 5
  • Grade 6
  • Grade 7
  • Grade 8
  • Grade 9
  • Grade 10
  • Grade 11
  • Grade 12

Keywords:

Informal Education,NSDL_SetSpec_ncs-NSDL-COLLECTION-000-003-112-021,Education,oai:nsdl.org:2200/20120724194932782T,NSDL,Technical Education (Lower Division),Undergraduate (Lower Division),Vocational Education -- Technical,Vocational Education -- Technology,Technical Education (Upper Division),Engineering,Higher Education,Vocational/Professional Development Education,Science -- Engineering,Technology,General Public,Science -- Technology

Language:

English

Access Privileges:

Public - Available to anyone

License Deed:

Creative Commons Attribution Non-Commercial Share Alike

Collections:

None
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