Type:

Other

Description:

In this lab activity from the Digital Logic Project, students design, test, and simulate a basic logic circuit using the Quartus II development software. The circuit created is a ripple-carry four-bit adder/subtractor using both behavioral and structural VHDL coding.

Subjects:

  • Science > Engineering
  • Science > Technology
  • Education > General

Education Levels:

  • Grade 1
  • Grade 2
  • Grade 3
  • Grade 4
  • Grade 5
  • Grade 6
  • Grade 7
  • Grade 8
  • Grade 9
  • Grade 10
  • Grade 11
  • Grade 12

Keywords:

Informal Education,NSDL_SetSpec_ncs-NSDL-COLLECTION-000-003-112-021,Undergraduate (Lower Division),Education,NSDL,Technical Education (Lower Division),oai:nsdl.org:2200/20120724194934570T,Vocational Education -- Technical,Vocational Education -- Technology,Technical Education (Upper Division),Engineering,Higher Education,Vocational/Professional Development Education,Science -- Engineering,Technology,General Public,Science -- Technology

Language:

English

Access Privileges:

Public - Available to anyone

License Deed:

Creative Commons Attribution Non-Commercial Share Alike

Collections:

None
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