Type:

Other

Description:

This lab activity from the Digital Logic Project demonstrates many advanced VHDL techniques and how they can be used to your advantage to create efficient VHDL code. Topics include operator balancing, resource sharing, preventing unwanted latches, and state machine encoding schemes.

Subjects:

  • Science > Engineering
  • Science > Technology
  • Education > General

Education Levels:

  • Grade 1
  • Grade 2
  • Grade 3
  • Grade 4
  • Grade 5
  • Grade 6
  • Grade 7
  • Grade 8
  • Grade 9
  • Grade 10
  • Grade 11
  • Grade 12

Keywords:

Informal Education,NSDL_SetSpec_ncs-NSDL-COLLECTION-000-003-112-021,Education,NSDL,Technical Education (Lower Division),Undergraduate (Lower Division),Vocational Education -- Technical,Engineering,Vocational Education -- Technology,Technical Education (Upper Division),oai:nsdl.org:2200/20120724194933457T,Higher Education,Vocational/Professional Development Education,Science -- Engineering,Technology,General Public,Science -- Technology

Language:

English

Access Privileges:

Public - Available to anyone

License Deed:

Creative Commons Attribution Non-Commercial Share Alike

Collections:

None
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